clk: renesas: r9a08g046: Add SCIF{1..5} clocks and resets

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Add SCIF{1..5} clock and reset entries.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20260330132349.149391-5-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

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Biju Das 2026-03-30 14:23:41 +01:00 • committed by Geert Uytterhoeven

parent c03f83f2a3

commit 6b99bb5e6e

1 changed files with 15 additions and 0 deletions

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drivers/clk/renesas/r9a08g046-cpg.c

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