clk: renesas: r9a06g032: Switch to .determine_rate()

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As the .round_rate() callback returns a long clock rate, it cannot
return clock rates that do not fit in signed long, but do fit in
unsigned long.  Hence switch the divider clocks on RZ/N1 from the old
.round_rate() callback to the newer .determine_rate() callback, which
does not suffer from this limitation.

Note that range checking is not yet implemented.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/7a384d02b85cdaac4a0e2b357582c8244b9a6f98.1617282116.git.geert+renesas@glider.be

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Geert Uytterhoeven 2021-04-01 15:03:24 +02:00

parent 02c69593e6

commit 6bd913f54f

1 changed files with 13 additions and 12 deletions

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drivers/clk/renesas/r9a06g032-clocks.c

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