drm/i915/cx0_phy: Fix C10 pll programming sequence

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[ Upstream commit 385a95cc72 ]

According to spec VDR_CUSTOM_WIDTH register gets programmed after pll
specific VDR registers and TX Lane programming registers are done.
Moreover we only program into C10_VDR_CONTROL1 to update config and
setup master lane once all VDR registers are written into.

Bspec: 67636
Fixes: 51390cc0e0 ("drm/i915/mtl: Add Support for C10 PHY message bus and pll programming")
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20241216181554.2861381-1-suraj.kandpal@intel.com
(cherry picked from commit f9d418552b)
Signed-off-by: Tvrtko Ursulin <tursulin@ursulin.net>
Signed-off-by: Sasha Levin <sashal@kernel.org>

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Suraj Kandpal 2024-12-16 23:45:54 +05:30 • committed by Greg Kroah-Hartman

parent 9f6f54e6a6

commit 6bf65f3970

1 changed files with 4 additions and 8 deletions

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drivers/gpu/drm/i915/display/intel_cx0_phy.c

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