drm/amd/display: Raise dispclk value for dce_update_clocks

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[Why]

The DISPCLK value was previously requested to be 15% higher for all
ASICS that went through the dce110 bandwidth code path. As part of a
refactoring of dce_clocks and dce110 set_bandwidth this was removed
for power saving considerations.

This changed caused corruption under certain display configurations.
Originally thought to be Vega specific, it was also observed on Polaris.

[How]

The 15% is brought back but its placement differs from the original
patch. This boost should only be enable while DFS bypass is inactive.

This (like the Vega patch) is also a workaround that should be
removed after the root cause is identified.

Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

...

This commit is contained in:

Nicholas Kazlauskas 2018-09-21 09:35:24 -04:00 • committed by Alex Deucher

parent a37786abc3

commit 6c0984d53b

1 changed files with 5 additions and 0 deletions

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drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c

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