[ARM] Feroceon: speed up flushing of the entire cache

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Flushing the L1 D cache with a test/clean/invalidate loop is very
easy in software, but it is not the quickest way of doing it, as
there is a lot of overhead involved in re-scanning the cache from
the beginning every time we hit a dirty line.

This patch makes proc-feroceon.S use "clean+invalidate by set/way"
loops according to possible cache configuration of Feroceon CPUs
(either direct-mapped or 4-way set associative).

Signed-off-by: Nicolas Pitre <nico@marvell.com>
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>

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Nicolas Pitre 2008-04-24 02:04:54 +02:00 • committed by Lennert Buytenhek

parent 79e90dd5aa

commit 6c386e58aa

1 changed files with 48 additions and 11 deletions

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arch/arm/mm/proc-feroceon.S

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