clk: at91: pll: fix input range validity check

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The PLL impose a certain input range to work correctly, but it appears that
this input range does not apply on the input clock (or parent clock) but
on the input clock after it has passed the PLL divisor.
Fix the implementation accordingly.

Cc: <stable@vger.kernel.org> # v3.14+
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Reported-by: Jonas Andersson <jonas@microbit.se>

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Boris Brezillon 2015-03-27 23:53:15 +01:00

parent 03bc10ab5b

commit 6c7b03e1ae

1 changed files with 10 additions and 2 deletions

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drivers/clk/at91/clk-pll.c

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