fsl-usb: do not test for PHY_CLK_VALID bit on controller version 1.6

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commit d183c81929 upstream.

Per reference manuals of Freescale P1020 and P2020 SoCs, USB controller
present in these SoCs has bit 17 of USBx_CONTROL register marked as
Reserved - there is no PHY_CLK_VALID bit there.

Testing for this bit in ehci_fsl_setup_phy() behaves differently on two
P1020RDB boards available here - on one board test passes and fsl-usb
init succeeds, but on other board test fails, causing fsl-usb init to
fail.

This patch changes ehci_fsl_setup_phy() not to test PHY_CLK_VALID on
controller version 1.6 that (per manual) does not have this bit.

Signed-off-by: Nikita Yushchenko <nyushchenko@dev.rtsoft.ru>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

...

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Nikita Yushchenko 2014-04-28 19:23:44 +04:00 • committed by Greg Kroah-Hartman

parent edbfad5cee

commit 6cb00d58ad

1 changed files with 2 additions and 1 deletions

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drivers/usb/host/ehci-fsl.c

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