drm/fsl-dcu: fix endian issue when using clk_register_divider

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Since using clk_register_divider to setup the pixel clock, regmap
is no longer used. Regmap did take care of DCU using different
endianness. Check endianness using the device-tree property
"big-endian" to determine the location of DIV_RATIO.

Cc: stable@vger.kernel.org
Fixes: 2d701449bc ("drm/fsl-dcu: use common clock framework for pixel clock divider")
Reported-by: Meng Yi <meng.yi@nxp.com>
Signed-off-by: Stefan Agner <stefan@agner.ch>
Tested-by: Meng Yi <meng.yi@nxp.com>

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Stefan Agner 2016-09-02 11:23:37 -07:00

parent 2b2fd56d7e

commit 6cc4758ae9

1 changed files with 5 additions and 1 deletions

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drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c

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