RISC-V: Disable preemption before enabling interrupts

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Currently, irq is enabled before preemption disabling happens.
If the scheduler fired right here and cpu is scheduled then it
may blow up.

Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
[Atish: Commit text and code comment formatting update]
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Reviewed-by: Christoph Hellwig <hch@lst.de>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>

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Atish Patra 2018-10-02 12:14:58 -07:00 • committed by Palmer Dabbelt

parent b18d6f0525

commit 6db170ff4c

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1 changed files with 5 additions and 1 deletions

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6

arch/riscv/kernel/smpboot.c

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