media: Fix Lane mapping in Cadence CSI2TX

Browse source

This patch fixes mapping of lanes in DPHY_CFG register
of the controller. In the register, bit 0 means first data lane.
In Linux we currently assume lane 0 is clock.

Signed-off-by: Jan Kotas <jank@cadence.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>

...

This commit is contained in:

Jan Kotas 2019-07-22 04:22:22 -04:00 • committed by Mauro Carvalho Chehab

parent bf9df90b35

commit 6ded416d4a

1 changed files with 2 additions and 2 deletions

Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL

Download patch file Download diff file Expand all files Collapse all files

4

drivers/media/platform/cadence/cdns-csi2tx.c

View file