dt-bindings: perf: marvell: Add CN20K DDR PMU binding

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Marvell CN20K SoCs integrate a DDR Performance Monitoring Unit (PMU)
associated with the DDR controller. The block provides hardware counters
to monitor DDR traffic and performance events and is accessed via a
dedicated MMIO region.

The CN20K DDR PMU is functionally equivalent to the CN10K DDR PMU, with
minor register offset differences.

Signed-off-by: Geetha sowjanya <gakula@marvell.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Will Deacon <will@kernel.org>

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Geetha sowjanya 2026-06-01 13:03:16 +05:30 • committed by Will Deacon

parent fcc5eaea2d

commit 6e0aa591af

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Documentation/devicetree/bindings/perf/marvell-cn10k-ddr.yaml

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