drm/amd/display: update DCN2 uclk switch time

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[why]
value commited to by HW team is going to be higher
than pre-silicon, and will cause underflow if driver not
updated

[how]
update hardcoded value, update pstate switching logic
to fix case where with long uclk time we won't allow switch
even when we should

Signed-off-by: Jun Lei <Jun.Lei@amd.com>
Reviewed-by: Eric Yang <eric.yang2@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

...

This commit is contained in:

Jun Lei 2019-05-27 14:15:27 -04:00 • committed by Alex Deucher

parent cf020d49b3

commit 6e17b5b8a8

2 changed files with 9 additions and 5 deletions

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8

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

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6

drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h

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