dt-bindings: clock: versal-clk: Fix mio_clk index range in clock-names pattern

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The clock-names pattern "^mio_clk[00-77]+.*$" was intended to constrain
the MIO index to the valid range 00..77 (ZynqMP has 78 MIO pins),
but a regex character class cannot express a multi-digit decimal range.
Replace the bogus character class with an explicit alternation that
enumerates the two-digit decimal values 00..77.

Fixes: 03d4a10040 ("dt-bindings: clock: versal: Convert the xlnx,zynqmp-clk.txt to yaml")
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://patch.msgid.link/e742b7da70c2bf10650a81e537f1b90d76799416.1783516336.git.michal.simek@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>

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Michal Simek 2026-07-08 15:12:23 +02:00

parent 959393e81c

commit 6e32cb10cf

1 changed files with 1 additions and 1 deletions

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Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml

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