clk: meson: c3: pll: fix frac maximum value for hifi_pll

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The fractional denominator of C3's hifi_pll fractional multiplier is
fixed to 100000.

Fixes: 8a9a129dc5 ("clk: meson: c3: add support for the C3 SoC PLL clock")
Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>
Link: https://lore.kernel.org/r/20240909-fix_clk-v3-2-a6d8f6333c04@amlogic.com
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>

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Chuan Liu 2024-09-09 18:08:57 +08:00 • committed by Jerome Brunet

parent c939154e84

commit 6e442c2d78

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drivers/clk/meson/c3-pll.c

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