clk: sunxi-ng: a33: Set CLK_SET_RATE_PARENT for all audio module clocks

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All the audio interfaces on Allwinner SoCs need to change their module
clocks during operation, to switch between support for 44.1 kHz and 48
kHz family sample rates. The clock rate for the module clocks is
governed by their upstream audio PLL. The module clocks themselves only
have a gate, and sometimes a divider or mux. Thus any rate changes need
to be propagated upstream.

Set the CLK_SET_RATE_PARENT flag for all audio module clocks to achieve
this.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>

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Chen-Yu Tsai 2018-12-05 18:11:51 +08:00 • committed by Maxime Ripard

parent 37bb18398a

commit 6e6da2039c

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drivers/clk/sunxi-ng/ccu-sun8i-a33.c

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