irqchip/gic-v3: Ensure GICR_CTLR.EnableLPI=0 is observed before enabling

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Booting with GICR_CTLR.EnableLPI=1 is usually a bad idea, and may
result in subtle memory corruption. Detecting this is thus pretty
important.

On detecting that LPIs are still enabled, we taint the kernel (because
we're not sure of anything anymore), and try to disable LPIs. This can
fail, as implementations are allowed to implement GICR_CTLR.EnableLPI
as a one-way enable, meaning the redistributors cannot be reprogrammed
with new tables.

Should this happen, we fail probing the redistributor and warn the user
that things are pretty dire.

Signed-off-by: Shanker Donthineni <shankerd@codeaurora.org>
[maz: reworded changelog, minor comment and message changes]
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>

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Shanker Donthineni 2018-03-21 20:58:49 -05:00 • committed by Marc Zyngier

parent 19d9916448

commit 6eb486b66a

2 changed files with 61 additions and 14 deletions

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74

drivers/irqchip/irq-gic-v3-its.c

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1

include/linux/irqchip/arm-gic-v3.h

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