powerpc/mpc5200: PCI write combine timer

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On MPC5200 the PCI target control register (PCITCR) @ MBAR + 0xD6C is
initialized with only bit 7 (Latrule disable) set. The 8-Bit write
combine timer (Bits 24..31) should be also set to a reasonable value
_greater zero_ (0x08 = default) since setting it to 0x00 leads to
_very poor_ performance as a PCI target since external burst won't be
possible at all.

Setting the WCT to 0x08 (cache-line size) leads to good overall perfomance.

Signed-off-by: Andre Schwarz <andre.schwarz@matrix-vision.de>
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>

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Andre Schwarz 2008-07-10 11:53:16 +02:00 • committed by Grant Likely

parent 0db9360aaa

commit 6eb9d32298

1 changed files with 2 additions and 1 deletions

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arch/powerpc/platforms/52xx/mpc52xx_pci.c

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