xen: support 52 bit physical addresses in pv guests

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Physical addresses on processors supporting 5 level paging can be up to
52 bits wide. For a Xen pv guest running on such a machine those
physical addresses have to be supported in order to be able to use any
memory on the machine even if the guest itself does not support 5 level
paging.

So when reading/writing a MFN from/to a pte don't use the kernel's
PTE_PFN_MASK but a new XEN_PTE_MFN_MASK allowing full 40 bit wide MFNs.

Signed-off-by: Juergen Gross <jgross@suse.com>
Reviewed-by: Boris Ostrovsky <boris.ostrovsky@oracle.com>
Signed-off-by: Boris Ostrovsky <boris.ostrovsky@oracle.com>

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Juergen Gross 2017-10-27 19:49:37 +02:00 • committed by Boris Ostrovsky

parent 5eee149ab9

commit 6f0e8bf167

2 changed files with 12 additions and 3 deletions

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11

arch/x86/include/asm/xen/page.h

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4

arch/x86/xen/mmu_pv.c

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