drm/amd/pm/powerplay/smumgr: Fix PCIeBootLinkLevel value on Fiji

Browse source

[ Upstream commit 07a13f913c ]

Previously this was initialized with zero which represented PCIe Gen
1.0 instead of using the
maximum value from the speed table which is the behaviour of all other
smumgr implementations.

Fixes: 18edef19ea ("drm/amd/powerplay: implement fw image related smu interface for Fiji.")
Signed-off-by: John Smith <itistotalbotnet@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
(cherry picked from commit c52238c9fb)
Signed-off-by: Sasha Levin <sashal@kernel.org>

...

This commit is contained in:

John Smith 2025-10-21 11:08:13 +02:00 • committed by Greg Kroah-Hartman

parent 3545f3cb51

commit 6f18f14eb3

1 changed files with 1 additions and 1 deletions

Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL

Download patch file Download diff file Expand all files Collapse all files

2

drivers/gpu/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

View file