clk: socfpga: agilex: add nand_x_clk and nand_ecc_clk

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And the nand_x_clk and nand_ecc_clk. Make the nand_x_clk be the main
clock that is feeding the NAND IP and correct it's parent to be the
l4_mp_clk.

Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Link: https://lore.kernel.org/r/20200616202417.14376-2-dinguyen@kernel.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

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Dinh Nguyen 2020-06-16 15:24:16 -05:00 • committed by Stephen Boyd

parent c2710fdf93

commit 6f3bcf56f8

1 changed files with 5 additions and 1 deletions

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drivers/clk/socfpga/clk-agilex.c

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