drm/amd/display: Update get_pixel_clk_frequency() for DCN4x DCCG DP DTO

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[Why & How]
DCN4x ASICs have different DCCG logic for programming DP DTO. The current
get_pixel_clk_frequency_100hz() function does not account for this.

Rename the function to "get_dp_dto_frequency" to more accurately
reflect its intended behaviour. Create a new function that correctly
calculates the target pixel rate for DCN4.x DCCG design and use it.

Reviewed-by: Leo Chen <leo.chen@amd.com>
Signed-off-by: Ovidiu Bunea <ovidiu.bunea@amd.com>
Signed-off-by: Ray Wu <ray.wu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

...

This commit is contained in:

Ovidiu Bunea 2026-05-01 19:38:13 -04:00 • committed by Alex Deucher

parent 470d1ae31d

commit 6f6483dbfa

5 changed files with 83 additions and 21 deletions

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4

drivers/gpu/drm/amd/display/dc/core/dc.c

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85

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

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7

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h

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4

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

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4

drivers/gpu/drm/amd/display/dc/inc/clock_source.h

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