arm64: dts: renesas: r8a77990: Add secondary CA53 CPU core

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Add a device node for the second Cortex-A53 CPU core on the Renesas
R-Car E3 (r8a77990) SoC, and adjust the interrupt delivery masks for ARM
Generic Interrupt Controller and Architectured Timer.

Based on a patch in the BSP by Takeshi Kihara.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

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Geert Uytterhoeven 2018-06-05 19:17:13 +02:00 • committed by Simon Horman

parent eb614d9439

commit 7085f5d9e8

1 changed files with 18 additions and 9 deletions

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arch/arm64/boot/dts/renesas/r8a77990.dtsi

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