drm/i915: Store cdclk PLL reference clock under dev_priv

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Future platforms will have multiple options for the cdclk PLL reference
clock, so let's start tracking that under dev_priv alreday on SKL,
although on SKL it's always 24 MHz.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1463172100-24715-15-git-send-email-ville.syrjala@linux.intel.com
Reviewed-by: Imre Deak <imre.deak@intel.com>

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This commit is contained in:

Ville Syrjälä 2016-05-13 23:41:33 +03:00

parent 63911d7295

commit 709e05c3c4

2 changed files with 9 additions and 7 deletions

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2

drivers/gpu/drm/i915/i915_drv.h

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14

drivers/gpu/drm/i915/intel_display.c

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