drm/i915/icl: Calculate DPLL params for DSI

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This patch calculates various DPLL dividers and
parameters for DSI encoder and adjust AFE clock
for DSI. For DSI, 8x clock is AFE clock.

v2: Extend haswell_crtc_compute_clock() for Gen11 DSI

v3: Rebase

v4: use port clock instead of bitrate.

v5: Reabse and remove divide by 5

v6 by Jani:
- Fix indent (Madhav)
- Fix dpll state calc for EDP and DP MST

Co-developed-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/525d41d0d893dcdc8874d2ce70afa226227ea3f4.1543500285.git.jani.nikula@intel.com

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This commit is contained in:

Madhav Chauhan 2018-11-29 16:12:18 +02:00 • committed by Jani Nikula

parent 1dd07e56a3

commit 70a057b7d4

2 changed files with 5 additions and 2 deletions

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4

drivers/gpu/drm/i915/intel_display.c

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3

drivers/gpu/drm/i915/intel_dpll_mgr.c

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