clk: renesas: r9a07g044: Add ethernet clock sources

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Ethernet reference clock can be sourced from PLL5_FOUT3 or PLL6. Add
support for ethernet source clock selection using SEL_PLL_6_2 mux.

This patch also renames the PLL5_DIV2 core clock to PLL5_250 to match
with the register description as mentioned in RZ/G2L HW manual (Rev.1.00).

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20210922155145.28156-3-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

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This commit is contained in:

Biju Das 2021-09-22 16:51:43 +01:00 • committed by Geert Uytterhoeven

parent 7c5a256173

commit 70a4af3662

2 changed files with 21 additions and 1 deletions

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19

drivers/clk/renesas/r9a07g044-cpg.c

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3

drivers/clk/renesas/rzg2l-cpg.h

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