perf/x86: Don't assume there can be only 4 PEBS events

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On Sandy Bridge in non HT mode there are 8 counters available.
Since every counter can write a PEBS record assuming there are
4 max is incorrect. Use the reported counter number -- with an
upper limit for a static array -- instead.

Also I made the warning messages a bit more informational.

Signed-off-by: Andi Kleen <ak@linux.intel.com>
Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl>
Link: http://lkml.kernel.org/r/1338944211-28275-2-git-send-email-andi@firstfloor.org
Signed-off-by: Ingo Molnar <mingo@kernel.org>

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This commit is contained in:

Andi Kleen 2012-06-05 17:56:48 -07:00 • committed by Ingo Molnar

parent c48b60538c

commit 70ab7003de

3 changed files with 8 additions and 5 deletions

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3

arch/x86/kernel/cpu/perf_event.h

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2

arch/x86/kernel/cpu/perf_event_intel.c

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8

arch/x86/kernel/cpu/perf_event_intel_ds.c

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