[ARM] mv78xx0: force eth2/eth3 to PHYless mode on pre-A0 silicon

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On pre-A0 revisions of the mv78xx0 SoC, the third and fourth
ethernet interface are not brought out to pins, but are internally
cross-connected, so if we run on pre-A0 silicon, we'll force eth2
and eth3 to PHYless mode.

Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>

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Lennert Buytenhek 2009-02-20 02:31:58 +01:00 • committed by Nicolas Pitre

parent cfdeb6376e

commit 712424fd95

1 changed files with 27 additions and 0 deletions

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arch/arm/mach-mv78xx0/common.c

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