clk: sunxi-ng: a80: Fix audio PLL comment not matching actual code

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We ignore the d1 and d2 dividers in the audio PLL, and force them to
1 (register value 0) at probe time. However the comment preceding the
audio PLL definition says we enforce the default value, which is not
the same.

Fix the preceding comment to match what we do in code.

Fixes: b8eb71dcdd ("clk: sunxi-ng: Add A80 CCU")
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>

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Chen-Yu Tsai 2017-03-24 16:33:07 +08:00 • committed by Maxime Ripard

parent 95ad8ed9c8

commit 7149c1becd

1 changed files with 1 additions and 2 deletions

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drivers/clk/sunxi-ng/ccu-sun9i-a80.c

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