drm/i915/tgl: Use refclk/2 as bypass frequency

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Unlike gen11, which always ran at 50MHz when the cdclk PLL was disabled,
TGL runs at refclk/2.  The 50MHz croclk/2 is only used by hardware
during some power state transitions.

Bspec: 49201
Cc: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190905181337.23727-1-matthew.d.roper@intel.com
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

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This commit is contained in:

Matt Roper 2019-09-05 11:13:37 -07:00

parent ca9cab1834

commit 71cd86cfaa

1 changed files with 5 additions and 2 deletions

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7

drivers/gpu/drm/i915/display/intel_cdclk.c

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