clk: meson: migrate plls clocks to clk_regmap

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Rework meson pll driver to use clk_regmap and move meson8b, gxbb and
axg's clock using meson_clk_pll to clk_regmap.

This rework is not just about clk_regmap, there a serious clean-up of
the driver code:
* Add lock and reset field: Previously inferred from the n field.
* Simplify the reset logic: Code seemed to apply reset differently but
  in fact it was always the same -> assert reset, apply params,
  de-assert reset. The 2 lock checking loops have been kept for now, as
  they seem to be necessary.
* Do the sequence of init register pokes only at .init() instead of in
  .set_rate(). Redoing the init on every set_rate() is not necessary

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>

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This commit is contained in:

Jerome Brunet 2018-02-12 15:58:42 +01:00 • committed by Neil Armstrong

parent 88a4e12836

commit 722825dcd5

5 changed files with 535 additions and 530 deletions

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209

drivers/clk/meson/axg.c

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233

drivers/clk/meson/clk-pll.c

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36

drivers/clk/meson/clkc.h

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422

drivers/clk/meson/gxbb.c

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145

drivers/clk/meson/meson8b.c

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