clk: renesas: rcar-gen4: Add support for variable fractional PLLs

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The custom clock driver that models PLL clocks on R-Car Gen4 supports
PLL2 on R-Car V4H/V4M only, while PLL3, PLL4, and PLL6 use the same
control register layout.

Extend the existing support to PLL3, PLL4, and PLL6, and introduce a new
clock type and helper macro to describe these PLLs.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/84ead759782560ec5643711e6bdd787a751053ce.1721648548.git.geert+renesas@glider.be

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This commit is contained in:

Geert Uytterhoeven 2024-07-22 13:50:26 +02:00

parent 1b131e08e7

commit 724620bd71

2 changed files with 18 additions and 7 deletions

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21

drivers/clk/renesas/rcar-gen4-cpg.c

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4

drivers/clk/renesas/rcar-gen4-cpg.h

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