riscv: dts: starfive: jh7110-common: add CPU BUS PERH QSPI clocks to syscrg

Browse source

Add syscrg clock assignments for CPU, BUS, PERH, and QSPI as required by
boot loader before kernel.

Signed-off-by: E Shattow <e@freeshell.de>
Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>

...

This commit is contained in:

E Shattow 2025-05-02 03:30:41 -07:00 • committed by Conor Dooley

parent 71385a893c

commit 724a6718ce

1 changed files with 10 additions and 2 deletions

Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL

Download patch file Download diff file Expand all files Collapse all files

12

arch/riscv/boot/dts/starfive/jh7110-common.dtsi

View file