drm: rcar-du: Rework clock configuration based on hardware limits

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The DU channels that have a display PLL (DPLL) can only use external
clock sources, and don't have an internal clock divider (with the
exception of H3 ES1.x where the post-divider is present and needs to be
used as a workaround for a DPLL silicon issue).

Rework the clock configuration to take this into account, avoiding
selection of non-existing clock sources or usage of a missing
post-divider.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Reviewed-by: Jacopo Mondi <jacopo+renesas@jmondi.org>

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Laurent Pinchart 2018-07-27 15:29:08 +03:00

parent c6e3194a3b

commit 7281e6c6a5

1 changed files with 73 additions and 61 deletions

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148

drivers/gpu/drm/rcar-du/rcar_du_crtc.c

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