drm/radeon: Always flush the HDP cache before submitting a CS to the GPU

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This ensures the GPU sees all previous CPU writes to VRAM, which makes it
safe:

* For userspace to stream data from CPU to GPU via VRAM instead of GTT
* For IBs to be stored in VRAM instead of GTT
* For ring buffers to be stored in VRAM instead of GTT, if the HPD flush
  is performed via MMIO

Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

...

This commit is contained in:

Michel Dänzer 2014-07-31 18:43:49 +09:00 • committed by Alex Deucher

parent 124764f174

commit 72a9987edc

7 changed files with 35 additions and 13 deletions

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4

drivers/gpu/drm/radeon/cik.c

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20

drivers/gpu/drm/radeon/r100.c

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1

drivers/gpu/drm/radeon/radeon.h

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6

drivers/gpu/drm/radeon/radeon_asic.c

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3

drivers/gpu/drm/radeon/radeon_asic.h

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4

drivers/gpu/drm/radeon/radeon_drv.c

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10

drivers/gpu/drm/radeon/radeon_ring.c

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