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drm/amd/display: Split OPTC_PIPE_CONTROL_LOCK into smaller HWSS blocks

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[why]
Block level sequence operations should not use global state structs such
as pipe_ctx. OPTC_PIPE_CONTROL_LOCK is a BLS with complex logic
dispatching a lot of smaller hardware programming operations.
BLS should be a simple and atomic hardware operation without performing
mutations or having an access to global state. All operations on global
state should be moved to build step in HWSS.

[how]
- Split OPTC_PIPE_CONTROL_LOCK into substeps:
	- HUBP_WAIT_FLIP_PENDING,
	- TG_SET_GSL,
	- TG_SET_GSL_SOURCE_SELECT,
	- TG_LOCK,
	- TG_3DLUT_WA_UNLOCK.
- Add hwss_pipe_control_lock - for in place build + execution.
- Remove timeout from HUBP_WAIT_FOR_FLIP_PENDING.
- Move software logic to builder. which fills pipe_control_lock_params
  containing data for programming actual hwss blocks.
- Due to differences in what pipe control lock means bettween
  asics following builder variants are added:
	- dce_build_pipe_control_lock_sequence for asics pre DCN20,
	- dcn20_build_pipe_control_lock_sequence.
- Rework gsl group programming to use builder / executor pattern.

Reviewed-by: Alvin Lee <alvin.lee2@amd.com>
Signed-off-by: Tomasz Siemek <tomasz.siemek@amd.com>
Signed-off-by: Ivan Lipski <ivan.lipski@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Tomasz Siemek 2026-08-11 11:46:13 +02:00 • committed by Alex Deucher
commit 72cc718d4c
32 changed files with 367 additions and 316 deletions
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8
drivers/gpu/drm/amd/display/dc/core/dc.c
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125
drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
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46
drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.c
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12
drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.h
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5
drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
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5
drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c
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3
drivers/gpu/drm/amd/display/dc/hwss/dce80/dce80_hwseq.c
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31
drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
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5
drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h
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4
drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_init.c
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153
drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
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14
drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h
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drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_init.c
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34
drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c
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5
drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.h
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drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_init.c
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3
drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_init.c
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3
drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_init.c
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3
drivers/gpu/drm/amd/display/dc/hwss/dcn301/dcn301_init.c
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3
drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_init.c
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3
drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_init.c
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4
drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
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3
drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_init.c
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3
drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_init.c
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3
drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_init.c
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140
drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
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3
drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h
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3
drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_init.c
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3
drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_init.c
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3
drivers/gpu/drm/amd/display/dc/hwss/dcn60/dcn60_init.c
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43
drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h
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3
drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h
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