usb: dwc3: exynos: Add provision for suspend clock

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DWC3 controller on Exynos SoC series have separate control for
suspend clock which replaces pipe3_rx_pclk as clock source to
a small part of DWC3 core that operates when SS PHY is in its
lowest power state (P3) in states SS.disabled and U3.

Suggested-by: Anton Tikhomirov <av.tikhomirov@samsung.com>
Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>

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Vivek Gautam 2014-11-21 19:05:46 +05:30 • committed by Felipe Balbi

parent c1a3acaadd

commit 72d996fc7a

1 changed files with 11 additions and 0 deletions

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drivers/usb/dwc3/dwc3-exynos.c

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