clk: starfive: jh7110-sys: Add notifier for PLL0 clock

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commit 538d5477b2 upstream.

Add notifier function for PLL0 clock. In the function, the cpu_root clock
should be operated by saving its current parent and setting a new safe
parent (osc clock) before setting the PLL0 clock rate. After setting PLL0
rate, it should be switched back to the original parent clock.

Fixes: e2c510d6d6 ("riscv: dts: starfive: Add cpu scaling for JH7110 SoC")
Cc: stable@vger.kernel.org
Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
Link: https://lore.kernel.org/r/20240826080430.179788-2-xingyu.wu@starfivetech.com
Reviewed-by: Hal Feng <hal.feng@starfivetech.com>
Tested-by: Michael Jeanson <mjeanson@efficios.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

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This commit is contained in:

Xingyu Wu 2024-08-26 16:04:29 +08:00 • committed by Greg Kroah-Hartman

parent f36df5cc86

commit 72f4fc5fb2

2 changed files with 32 additions and 1 deletions

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31

drivers/clk/starfive/clk-starfive-jh7110-sys.c

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2

drivers/clk/starfive/clk-starfive-jh71x0.h

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