clk: vc5: Add bindings for IDT VersaClock 5P49V6901

Browse source

IDT VersaClock 6 5P49V6901 has 4 clock outputs, 4 fractional dividers.
Input clock source can be taken from either external crystal or from
external reference clock.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Alexey Firago <alexey_firago@mentor.com>
Cc: Rob Herring <robh@kernel.org>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Cc: linux-renesas-soc@vger.kernel.org
Cc: devicetree@vger.kernel.org
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>

...

This commit is contained in:

Marek Vasut 2017-07-09 15:28:13 +02:00 • committed by Stephen Boyd

parent 8c1ebe9762

commit 73100e79c7

1 changed files with 19 additions and 7 deletions

Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL

Download patch file Download diff file Expand all files Collapse all files

26

Documentation/devicetree/bindings/clock/idt,versaclock5.txt

View file