drm/i915/gt: Add workaround 14016712196

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[ Upstream commit d922b80b10 ]

For mtl, workaround suggests that, SW insert a
dummy PIPE_CONTROL prior to PIPE_CONTROL which
contains a post sync: Timestamp or Write Immediate.

Bspec: 72197

V5:
  - Remove ret variable - Andi
V4:
  - Update commit message, avoid returing cs - Andi/Matt
V3:
  - Wrap dummy pipe control stuff in API - Andi
V2:
  - Fix  kernel test robot warnings

Closes: https://lore.kernel.org/oe-kbuild-all/202305121525.3EWdGoBY-lkp@intel.com/
Signed-off-by: Tejas Upadhyay <tejas.upadhyay@intel.com>
Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com>
Reviewed-by: Andrzej Hajda <andrzej.hajda@intel.com>
Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230601110959.1715927-1-tejas.upadhyay@intel.com
Stable-dep-of: 592b228f12 ("drm/i915/gt: Rename flags with bit_group_X according to the datasheet")
Signed-off-by: Sasha Levin <sashal@kernel.org>

...

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Tejas Upadhyay 2023-06-01 16:39:59 +05:30 • committed by Greg Kroah-Hartman

parent 17b66e10b1

commit 73400908a9

1 changed files with 38 additions and 0 deletions

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drivers/gpu/drm/i915/gt/gen8_engine_cs.c

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