drm/i915: Update DSPCNTR gamma/csc bits during crtc_enable()

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On g4x+ we depend on the primary plane DSPCNTR gamma/csc enable
bits for the pipe bottom color. To guarantee that those are
correct already when enabling the crtc let's do an explicit
->disable_plane() call before enabling the pipe.

On skl+ this will be handled by the explicit PIPE_BOTTOM_COLOR
register which is already part of the normal color commit we
do durign crtc enable.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190207202146.26423-8-ville.syrjala@linux.intel.com

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This commit is contained in:

Ville Syrjälä 2019-02-07 22:21:46 +02:00

parent 02c52f1ed2

commit 73a116be68

2 changed files with 21 additions and 0 deletions

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4

drivers/gpu/drm/i915/intel_color.c

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17

drivers/gpu/drm/i915/intel_display.c

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