drm/xe/pvc: Force even num engines to use 64B

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Wa_16017236439 requires that we update BCS_SWCTRL
(via indirect context batch buffer) to set 64B
transfers when running on an even-numbered BCS
engine and 256B on an odd-numbered BCS engine.

v2: Move WA from engine_was[] to lrc_was[]

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Tejas Upadhyay <tejas.upadhyay@intel.com>
Signed-off-by: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

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Niranjana Vishwanathapura 2023-07-18 10:45:28 +00:00 • committed by Rodrigo Vivi

parent 25063811d9

commit 7407f2e5c3

2 changed files with 11 additions and 0 deletions

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1

drivers/gpu/drm/xe/regs/xe_engine_regs.h

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10

drivers/gpu/drm/xe/xe_wa.c

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