drm/amdgpu: revise the mode2 reset for vangogh

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PCIE MMIO bar needs to be restored firstly after the reset event
triggers. So it's unable to access the registers to wait for response
from SMU. Becasue the value of mmMP1_SMN_C2PMSG_90 is invalid at that
moment.

Signed-off-by: Huang Rui <ray.huang@amd.com>
Acked-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

...

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Huang Rui 2020-12-02 15:28:23 +08:00 • committed by Alex Deucher

parent b6903089a5

commit 743538838c

3 changed files with 47 additions and 22 deletions

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22

drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

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45

drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c

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2

drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h

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