drm/i915: Program correct m n tu register for Valleyview

Browse source

m n tu register offset has changed in Valleyview. Also fixed DP limit
frequencies.

Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@intel.com>
Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
Acked-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

...

This commit is contained in:

Vijay Purushothaman 2012-09-27 19:13:04 +05:30 • committed by Daniel Vetter

parent b56747aace

commit 74a4dd2e45

2 changed files with 8 additions and 3 deletions

Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL

Download patch file Download diff file Expand all files Collapse all files

6

drivers/gpu/drm/i915/intel_display.c

View file

5

drivers/gpu/drm/i915/intel_dp.c

View file