iommu/arm-smmu-v3-sva: Enable Hardware Access and Hardware Dirty bits

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HTTU is introduced by utilizing the Dirty Bit Modifier (DBM) in the PTE.
When kernel maps a clean but writable page, it will set PTE_READONLY and
PTE_DBM (aka PTE_WRITE) at the same time. When a write occurs, an HTTU-
capable MMU will automatically clear the PTE_RDONLY bit without software
intervention.

On the other hand, SMMU has the same HTTU feature, yet it is not enabled
in the SVA CD. As a result, SMMU will not clear the PTE_RDONLY bit while
sharing the CPU page table, resulting in unnecessary stalls.

Thus, enable CTXDESC_CD_0_TCR_HA and CTXDESC_CD_0_TCR_HD in the SVA CD.

Suggested-by: Jason Gunthorpe <jgg@nvidia.com>
Signed-off-by: Nicolin Chen <nicolinc@nvidia.com>
Signed-off-by: Will Deacon <will@kernel.org>

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Nicolin Chen 2026-05-03 06:54:12 -07:00 • committed by Will Deacon

parent be0d0b8588

commit 74fa4c177a

1 changed files with 10 additions and 0 deletions

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drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c

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