soc: sifive: ccache: fix missing free_irq() in error path in sifive_ccache_init()

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Add missing free_irq() before return error from sifive_ccache_init().

Fixes: a967a289f1 ("RISC-V: sifive_l2_cache: Add L2 cache controller driver for SiFive SoCs")
Signed-off-by: Yang Yingliang <yangyingliang@huawei.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>

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Yang Yingliang 2022-10-18 10:31:48 +08:00 • committed by Conor Dooley

parent 73e770f085

commit 756344e7cb

1 changed files with 4 additions and 1 deletions

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drivers/soc/sifive/sifive_ccache.c

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