drm/amd/display: Fix DPP PRE_GAM register offset on DCN60

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[WHY]
dcn60 uses dpp50_set_pregam_state, which reads PRE_GAM through the
dcn50_dpp_registers layout. PRE_GAM sat at a different offset in
dcn50 (based on DCN401) vs dcn60 (based on DCN42), so the cast
landed on the wrong register which causes the wrong address to be
used

[HOW]
Rebase the DPP macro inheritance so PRE_GAM shares a common offset:
DCN50 lists now inherit from DCN42, and DCN60 lists inherit from
DCN50. The dcn60 struct layout is unchanged, so PRE_GAM aligns
between the two and dpp50_set_pregam_state programs the correct
address.

Reviewed-by: Taimur Hassan <syed.hassan@amd.com>
Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com>
Signed-off-by: Alex Hung <alex.hung@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

...

This commit is contained in:

Alvin Lee 2026-08-17 17:13:17 -04:00 • committed by Alex Deucher

parent f0689a64cb

commit 75a139cb8b

2 changed files with 8 additions and 10 deletions

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11

drivers/gpu/drm/amd/display/dc/dpp/dcn50/dcn50_dpp.h

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7

drivers/gpu/drm/amd/display/dc/dpp/dcn60/dcn60_dpp.h

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