clk: meson: gxbb: fix wrong clock for SARADC/SANA

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According to the datasheet, in Meson-GXBB/GXL series,
The clock gate bit for SARADC is HHI_GCLK_MPEG2 bit[22],
while clock gate bit for SANA is HHI_GCLK_MPEG0 bit[10].

Test passed at gxl-s905x-p212 board.

The following published datasheets are wrong and should be updated
[1] GXBB v1.1.4
[2] GXL v0.3_20170314

Fixes: 738f66d321 ("clk: gxbb: add AmLogic GXBB clk controller driver")
Tested-by: Xingyu Chen <xingyu.chen@amlogic.com>
Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>

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Yixun Lan 2017-11-07 22:12:23 +08:00 • committed by Jerome Brunet

parent 4fbd8d194f

commit 75eccf5ed8

1 changed files with 2 additions and 2 deletions

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drivers/clk/meson/gxbb.c

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