drm/msm/dsi: fix check-before-set in the 7nm dsi_pll code

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[ Upstream commit 3b24cdfc72 ]

Fix setting min/max DSI PLL rate for the V4.1 7nm DSI PLL (used on
sm8250). Current code checks for pll->type before it is set (as it is
set in the msm_dsi_pll_init() after calling device-specific functions.

Cc: Jonathan Marek <jonathan@marek.ca>
Fixes: 1ef7c99d14 ("drm/msm/dsi: add support for 7nm DSI PHY/PLL")
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Rob Clark <robdclark@chromium.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>

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Dmitry Baryshkov 2021-02-25 01:47:51 +03:00 • committed by Greg Kroah-Hartman

parent 126aa8f234

commit 7637048707

3 changed files with 8 additions and 5 deletions

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2

drivers/gpu/drm/msm/dsi/pll/dsi_pll.c

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6

drivers/gpu/drm/msm/dsi/pll/dsi_pll.h

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5

drivers/gpu/drm/msm/dsi/pll/dsi_pll_7nm.c

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