x86/PCI: Use generic cacheline sizing instead of per-vendor tests.

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Instead of the PCI code needing to have code to determine the
cacheline size of each processor, use the data the cpu identification
code should have already determined during early boot.

(The vendor checks are also incomplete, and don't take into account
 modern CPUs)

I've been carrying a variant of this code in Fedora for a while,
that prints debug information.  There are a number of cases where we
are currently setting the PCI cacheline size to 32 bytes, when the CPU
cacheline size is 64 bytes.  With this patch, we set them both the same.

Signed-off-by: Dave Jones <davej@redhat.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>

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Dave Jones 2009-10-14 16:31:39 -04:00 • committed by Jesse Barnes

parent 98e724c791

commit 76b1a87b21

1 changed files with 11 additions and 7 deletions

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arch/x86/pci/common.c

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