drm/amd/display: Allocate zero bw after bw alloc enable

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[Why]
During DP tunnel creation, CM preallocates BW and reduces
estimated BW of other DPIA. CM release preallocation only
when allocation is complete. Display mode validation logic
validates timings based on bw available per host router.
In multi display setup, this causes bw allocation failure
when allocation greater than estimated bw.

[How]
Do zero alloc to make the CM to release preallocation and
update estimated BW correctly for all DPIAs per host router.

Reviewed-by: PeiChen Huang <peichen.huang@amd.com>
Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Meenakshikumar Somasundaram <meenakshikumar.somasundaram@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

...

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Meenakshikumar Somasundaram 2024-04-10 10:46:35 -04:00 • committed by Alex Deucher

parent 81f3d3c9a0

commit 771c75ad0b

1 changed files with 9 additions and 1 deletions

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drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.c

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